Hamming error correcting code generator and receiver

Error correcting codes are essential for an error-free data communication system. In this regard, forward error correcting codes (FEC) are better for a system, as the receiver system is prepared to handle errors. Moreover, FECs prevent the redundancy of transmitting erroneous data back to the transmitters end for correction. This was the inspiration to create a simple error correcting scheme based upon the least Hamming distance principle

With this end in view, I had implemented a proof of concept system that can correct a single bit error per six transmitted bits. The parameters of the coding scheme are hard coded to keep the system simple and minimal enough to display the basic working principle. However those system parameters can be easily incorporated as system inputs. This project contains the following:

1. Behavioral description of the system in verilog
2. RTL synthesis step
3. Physical design step and validation
4. Design Rule Check and Layout Versus Schematic

The entire system was implemented using Verilog by software packages of Cadence Design Systems.

The Project Report Preview

The project report is provided below: