A binary multiplier is an electronic circuit that is used in multiplication of two binary numbers in digital electronics such as computer. The traditional way of multiplication consists of multiplying each bit of multiplicand with multiplier and then summing up the partial products together. Booth’s multiplication algorithm provides a faster process, reducing the 8 partial products needed for a traditional 8 bit by 8 bit multiplier down to 4. This was the inspiration to design an 8 by 8 Booth encoded multiplier using the Cadence Virtuoso platform, with a Ripple-Carry adder used to sum the partial products.

With this end in view, we had implemented the multiplier from the basic building blocks of digital logic circuits, i.e MOSFETs, designing both the schematic and the layout of the circuit. This project contains the following:

Schematic design of the Booth encoder, Booth decoder and Ripple-Carry adder
Functional verification of each building block against the timing diagram
Layout design and layout area minimization
Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification

The entire system was implemented using the Cadence® Virtuoso® Analog Design Environment.

Here, the booth multiplier that we have implemented is functionally correct as we can see from the timing diagram. Also the circuit area has been minimized, as we tried to make it as compact as possible. We used transmission gates for XOR gate, to minimize delay . Also, the circuit only has 2 Layers of wires. These two layers also ensured that there was minimal propagation delay and less errors.

The Project Report Preview

The project report is provided below: